685 lines
42 KiB
Plaintext
685 lines
42 KiB
Plaintext
Release 14.1 - xst P.15xf (nt)
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Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.12 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.12 secs
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--> Reading design: main.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) Partition Resource Summary
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9.3) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "main.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "main"
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Output Format : NGC
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Target Device : xc3s250e-5-cp132
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---- Source Options
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Top Module Name : main
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : Yes
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : Yes
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Multiplier Style : Auto
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 100000
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Add Generic Clock Buffer(BUFG) : 24
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Register Duplication : YES
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Slice Packing : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Yes
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Use Synchronous Set : Yes
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Use Synchronous Reset : Yes
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Pack IO Registers into IOBs : Auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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Verilog 2001 : YES
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "C:/fpga/pong/speaker.vhd" in Library work.
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Architecture behavioral of Entity speaker is up to date.
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Compiling vhdl file "C:/fpga/pong/vga.vhd" in Library work.
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Architecture behavioral of Entity vga is up to date.
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Compiling vhdl file "C:/fpga/pong/main.vhd" in Library work.
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Entity <main> compiled.
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Entity <main> (Architecture <behavioral>) compiled.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for entity <main> in library <work> (architecture <behavioral>).
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Analyzing hierarchy for entity <speaker> in library <work> (architecture <behavioral>).
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Analyzing hierarchy for entity <vga> in library <work> (architecture <behavioral>).
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing Entity <main> in library <work> (Architecture <behavioral>).
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WARNING:Xst:819 - "C:/fpga/pong/main.vhd" line 85: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
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<w>, <y>, <x>
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Entity <main> analyzed. Unit <main> generated.
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Analyzing Entity <speaker> in library <work> (Architecture <behavioral>).
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Entity <speaker> analyzed. Unit <speaker> generated.
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Analyzing Entity <vga> in library <work> (Architecture <behavioral>).
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Entity <vga> analyzed. Unit <vga> generated.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit <speaker>.
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Related source file is "C:/fpga/pong/speaker.vhd".
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Found 25-bit register for signal <prescaler>.
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Found 25-bit adder for signal <prescaler$add0000> created at line 33.
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Found 1-bit register for signal <sout>.
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Found 25-bit comparator greatequal for signal <sout$cmp_ge0000> created at line 29.
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Summary:
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inferred 26 D-type flip-flop(s).
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inferred 1 Adder/Subtractor(s).
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inferred 1 Comparator(s).
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Unit <speaker> synthesized.
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Synthesizing Unit <vga>.
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Related source file is "C:/fpga/pong/vga.vhd".
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Found 1-bit register for signal <HS>.
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Found 1-bit register for signal <W>.
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Found 10-bit register for signal <X>.
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Found 10-bit register for signal <Y>.
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Found 1-bit register for signal <FRAME>.
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Found 1-bit register for signal <VS>.
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Found 8-bit register for signal <RGB>.
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Found 10-bit up counter for signal <horiz>.
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Found 11-bit comparator greater for signal <HS$cmp_gt0000> created at line 43.
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Found 11-bit comparator less for signal <HS$cmp_lt0000> created at line 43.
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Found 10-bit up counter for signal <vert>.
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Found 11-bit comparator greater for signal <VS$cmp_gt0000> created at line 49.
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Found 11-bit comparator less for signal <VS$cmp_lt0000> created at line 49.
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Found 11-bit comparator greatequal for signal <W$cmp_ge0000> created at line 32.
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Found 11-bit comparator greatequal for signal <W$cmp_ge0001> created at line 32.
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Found 11-bit comparator less for signal <W$cmp_lt0000> created at line 32.
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Found 11-bit comparator less for signal <W$cmp_lt0001> created at line 32.
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Found 10-bit adder for signal <X$add0000> created at line 36.
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Found 10-bit subtractor for signal <X$addsub0000> created at line 36.
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Found 10-bit adder for signal <Y$add0000> created at line 37.
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Found 10-bit subtractor for signal <Y$addsub0000> created at line 37.
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Summary:
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inferred 2 Counter(s).
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inferred 32 D-type flip-flop(s).
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inferred 4 Adder/Subtractor(s).
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inferred 8 Comparator(s).
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Unit <vga> synthesized.
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Synthesizing Unit <main>.
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Related source file is "C:/fpga/pong/main.vhd".
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WARNING:Xst:653 - Signal <ph> is used but never assigned. This sourceless signal will be automatically connected to value 00100000.
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WARNING:Xst:653 - Signal <cw> is used but never assigned. This sourceless signal will be automatically connected to value 00001010.
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WARNING:Xst:737 - Found 8-bit latch for signal <inrgb>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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Found 6-bit register for signal <cdx>.
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Found 6-bit adder for signal <cdx$addsub0000> created at line 129.
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Found 6-bit adder for signal <cdx$sub0000> created at line 105.
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Found 6-bit adder for signal <cdx$sub0001> created at line 121.
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Found 6-bit register for signal <cdy>.
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Found 6-bit adder for signal <cdy$sub0000> created at line 113.
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Found 11-bit up accumulator for signal <cx>.
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Found 11-bit up accumulator for signal <cy>.
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Found 25-bit register for signal <hper>.
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Found 11-bit adder for signal <hper$add0000> created at line 124.
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Found 11-bit adder for signal <hper$add0001> created at line 116.
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Found 11-bit subtractor for signal <hper$sub0000> created at line 124.
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Found 11-bit subtractor for signal <hper$sub0001> created at line 116.
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Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0000> created at line 161.
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Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0001> created at line 161.
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Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0002> created at line 162.
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Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0003> created at line 162.
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Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0004> created at line 164.
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Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0005> created at line 164.
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Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0006> created at line 166.
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Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0007> created at line 166.
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Found 11-bit comparator lessequal for signal <inrgb$cmp_le0000> created at line 161.
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Found 11-bit comparator lessequal for signal <inrgb$cmp_le0001> created at line 161.
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Found 11-bit comparator lessequal for signal <inrgb$cmp_le0002> created at line 162.
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Found 11-bit comparator lessequal for signal <inrgb$cmp_le0003> created at line 162.
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Found 11-bit comparator lessequal for signal <inrgb$cmp_le0004> created at line 164.
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Found 11-bit comparator lessequal for signal <inrgb$cmp_le0005> created at line 164.
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Found 11-bit comparator lessequal for signal <inrgb$cmp_le0006> created at line 166.
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Found 11-bit comparator lessequal for signal <inrgb$cmp_le0007> created at line 166.
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Found 11-bit updown accumulator for signal <lp>.
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Found 11-bit comparator greatequal for signal <lp$cmp_ge0000> created at line 134.
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Found 6-bit comparator greatequal for signal <lp$cmp_ge0001> created at line 132.
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Found 11-bit comparator greater for signal <lp$cmp_gt0000> created at line 133.
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Found 11-bit comparator lessequal for signal <lp$cmp_le0000> created at line 133.
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Found 11-bit subtractor for signal <lp$sub0000> created at line 134.
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Found 19-bit register for signal <prescaler>.
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Found 11-bit adder for signal <prescaler$add0000> created at line 124.
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Found 11-bit adder for signal <prescaler$add0001> created at line 124.
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Found 11-bit adder for signal <prescaler$add0002> created at line 116.
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Found 11-bit adder for signal <prescaler$add0003> created at line 124.
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Found 19-bit adder for signal <prescaler$addsub0000> created at line 151.
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Found 11-bit comparator greatequal for signal <prescaler$cmp_ge0000> created at line 124.
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Found 11-bit comparator greatequal for signal <prescaler$cmp_ge0001> created at line 124.
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Found 11-bit comparator greatequal for signal <prescaler$cmp_ge0002> created at line 116.
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Found 11-bit comparator greatequal for signal <prescaler$cmp_ge0003> created at line 116.
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Found 11-bit comparator greatequal for signal <prescaler$cmp_ge0004> created at line 108.
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Found 11-bit comparator greatequal for signal <prescaler$cmp_ge0005> created at line 100.
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Found 11-bit comparator lessequal for signal <prescaler$cmp_le0000> created at line 124.
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Found 11-bit comparator lessequal for signal <prescaler$cmp_le0001> created at line 124.
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Found 11-bit comparator lessequal for signal <prescaler$cmp_le0002> created at line 116.
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Found 11-bit comparator lessequal for signal <prescaler$cmp_le0003> created at line 116.
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Found 11-bit comparator lessequal for signal <prescaler$cmp_le0004> created at line 108.
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Found 11-bit comparator lessequal for signal <prescaler$cmp_le0005> created at line 100.
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Found 11-bit subtractor for signal <prescaler$sub0000> created at line 124.
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Found 11-bit subtractor for signal <prescaler$sub0001> created at line 116.
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Found 11-bit subtractor for signal <prescaler$sub0002> created at line 116.
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Found 11-bit subtractor for signal <prescaler$sub0003> created at line 124.
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Found 11-bit updown accumulator for signal <rp>.
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Found 11-bit comparator greatequal for signal <rp$cmp_ge0000> created at line 140.
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Found 11-bit comparator greater for signal <rp$cmp_gt0000> created at line 139.
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Found 11-bit comparator lessequal for signal <rp$cmp_le0000> created at line 139.
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Found 6-bit comparator less for signal <rp$cmp_lt0000> created at line 132.
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Found 11-bit subtractor for signal <rp$sub0000> created at line 140.
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Found 1-bit register for signal <son>.
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Found 20-bit comparator greatequal for signal <son$cmp_ge0000> created at line 147.
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Found 11-bit comparator greater for signal <son$cmp_gt0000> created at line 100.
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Found 11-bit comparator greater for signal <son$cmp_gt0001> created at line 108.
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Found 11-bit comparator greater for signal <son$cmp_gt0002> created at line 116.
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Found 11-bit comparator greater for signal <son$cmp_gt0003> created at line 116.
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Found 11-bit comparator greater for signal <son$cmp_gt0004> created at line 124.
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Found 11-bit comparator greater for signal <son$cmp_gt0005> created at line 124.
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Found 11-bit comparator less for signal <son$cmp_lt0000> created at line 100.
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Found 11-bit comparator less for signal <son$cmp_lt0001> created at line 108.
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Found 11-bit comparator less for signal <son$cmp_lt0002> created at line 116.
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Found 11-bit comparator less for signal <son$cmp_lt0003> created at line 116.
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Found 11-bit comparator less for signal <son$cmp_lt0004> created at line 124.
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Found 11-bit comparator less for signal <son$cmp_lt0005> created at line 124.
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Found 20-bit comparator less for signal <son$cmp_lt0006> created at line 147.
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Summary:
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inferred 4 Accumulator(s).
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inferred 57 D-type flip-flop(s).
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inferred 19 Adder/Subtractor(s).
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inferred 50 Comparator(s).
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Unit <main> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 24
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10-bit adder : 2
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10-bit subtractor : 2
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11-bit adder : 6
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11-bit subtractor : 8
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19-bit adder : 1
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25-bit adder : 1
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6-bit adder : 4
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# Counters : 2
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10-bit up counter : 2
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# Accumulators : 4
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11-bit up accumulator : 2
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11-bit updown accumulator : 2
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# Registers : 14
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1-bit register : 6
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10-bit register : 2
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19-bit register : 1
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25-bit register : 2
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6-bit register : 2
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8-bit register : 1
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# Latches : 1
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8-bit latch : 1
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# Comparators : 59
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11-bit comparator greatequal : 18
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11-bit comparator greater : 10
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11-bit comparator less : 10
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11-bit comparator lessequal : 16
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20-bit comparator greatequal : 1
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20-bit comparator less : 1
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25-bit comparator greatequal : 1
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6-bit comparator greatequal : 1
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6-bit comparator less : 1
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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WARNING:Xst:1293 - FF/Latch <hper_24> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_23> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_22> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_21> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_20> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_19> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_18> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_17> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_16> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_15> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_14> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_13> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_10> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_9> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_8> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_7> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_6> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_5> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_4> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_3> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_2> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_1> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_0> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 24
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10-bit adder : 2
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10-bit subtractor : 2
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11-bit adder : 6
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11-bit subtractor : 8
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19-bit adder : 1
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25-bit adder : 1
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6-bit adder : 4
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# Counters : 2
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10-bit up counter : 2
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# Accumulators : 4
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11-bit up accumulator : 2
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11-bit updown accumulator : 2
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# Registers : 115
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Flip-Flops : 115
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# Latches : 1
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8-bit latch : 1
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# Comparators : 59
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11-bit comparator greatequal : 18
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11-bit comparator greater : 10
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11-bit comparator less : 10
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11-bit comparator lessequal : 16
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20-bit comparator greatequal : 1
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20-bit comparator less : 1
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25-bit comparator greatequal : 1
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6-bit comparator greatequal : 1
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6-bit comparator less : 1
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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WARNING:Xst:1293 - FF/Latch <hper_24> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_23> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_22> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_21> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_20> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_19> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_18> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <hper_17> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <hper_16> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <hper_15> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <hper_14> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <hper_13> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <hper_10> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <hper_9> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <hper_8> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <hper_7> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <hper_6> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <hper_5> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <hper_4> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <hper_3> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <hper_2> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <hper_1> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <hper_0> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
INFO:Xst:2261 - The FF/Latch <hper_11> in Unit <main> is equivalent to the following FF/Latch, which will be removed : <hper_12>
|
|
INFO:Xst:2261 - The FF/Latch <7> in Unit <LPM_LATCH_1> is equivalent to the following 7 FFs/Latches, which will be removed : <6> <5> <4> <3> <2> <1> <0>
|
|
WARNING:Xst:1293 - FF/Latch <cdy_0> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <cdy_1> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
|
|
Optimizing unit <main> ...
|
|
WARNING:Xst:1293 - FF/Latch <cdx_0> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <cdx_1> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <cdx_2> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <cdx_1> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <cdx_2> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <cdx_1> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <cdx_2> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <cdx_1> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <cdx_2> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
|
|
|
|
Optimizing unit <speaker> ...
|
|
|
|
Optimizing unit <vga> ...
|
|
|
|
Mapping all equations...
|
|
Building and optimizing final netlist ...
|
|
INFO:Xst:2261 - The FF/Latch <VGADriver/RGB_7> in Unit <main> is equivalent to the following 7 FFs/Latches, which will be removed : <VGADriver/RGB_6> <VGADriver/RGB_5> <VGADriver/RGB_4> <VGADriver/RGB_3> <VGADriver/RGB_2> <VGADriver/RGB_1> <VGADriver/RGB_0>
|
|
Found area constraint ratio of 100 (+ 5) on block main, actual ratio is 13.
|
|
FlipFlop lp_5 has been replicated 1 time(s)
|
|
FlipFlop rp_5 has been replicated 1 time(s)
|
|
|
|
Final Macro Processing ...
|
|
|
|
=========================================================================
|
|
Final Register Report
|
|
|
|
Macro Statistics
|
|
# Registers : 145
|
|
Flip-Flops : 145
|
|
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* Partition Report *
|
|
=========================================================================
|
|
|
|
Partition Implementation Status
|
|
-------------------------------
|
|
|
|
No Partitions were found in this design.
|
|
|
|
-------------------------------
|
|
|
|
=========================================================================
|
|
* Final Report *
|
|
=========================================================================
|
|
Final Results
|
|
RTL Top Level Output File Name : main.ngr
|
|
Top Level Output File Name : main
|
|
Output Format : NGC
|
|
Optimization Goal : Speed
|
|
Keep Hierarchy : No
|
|
|
|
Design Statistics
|
|
# IOs : 20
|
|
|
|
Cell Usage :
|
|
# BELS : 1250
|
|
# GND : 1
|
|
# INV : 71
|
|
# LUT1 : 76
|
|
# LUT2 : 225
|
|
# LUT2_D : 2
|
|
# LUT2_L : 10
|
|
# LUT3 : 65
|
|
# LUT3_L : 3
|
|
# LUT4 : 127
|
|
# LUT4_D : 4
|
|
# LUT4_L : 6
|
|
# MUXCY : 404
|
|
# MUXF5 : 7
|
|
# VCC : 1
|
|
# XORCY : 248
|
|
# FlipFlops/Latches : 146
|
|
# FD : 25
|
|
# FDE : 68
|
|
# FDR : 40
|
|
# FDRE : 12
|
|
# LD : 1
|
|
# Clock Buffers : 2
|
|
# BUFG : 1
|
|
# BUFGP : 1
|
|
# IO Buffers : 19
|
|
# OBUF : 19
|
|
=========================================================================
|
|
|
|
Device utilization summary:
|
|
---------------------------
|
|
|
|
Selected Device : 3s250ecp132-5
|
|
|
|
Number of Slices: 314 out of 2448 12%
|
|
Number of Slice Flip Flops: 146 out of 4896 2%
|
|
Number of 4 input LUTs: 589 out of 4896 12%
|
|
Number of IOs: 20
|
|
Number of bonded IOBs: 20 out of 92 21%
|
|
Number of GCLKs: 2 out of 24 8%
|
|
|
|
---------------------------
|
|
Partition Resource Summary:
|
|
---------------------------
|
|
|
|
No Partitions were found in this design.
|
|
|
|
---------------------------
|
|
|
|
|
|
=========================================================================
|
|
TIMING REPORT
|
|
|
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
|
GENERATED AFTER PLACE-and-ROUTE.
|
|
|
|
Clock Information:
|
|
------------------
|
|
-----------------------------------+------------------------+-------+
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
|
-----------------------------------+------------------------+-------+
|
|
VGADriver/FRAME1 | BUFG | 74 |
|
|
VGADriver/W | NONE(inrgb_7) | 1 |
|
|
CLK | BUFGP | 71 |
|
|
-----------------------------------+------------------------+-------+
|
|
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
|
|
|
Asynchronous Control Signals Information:
|
|
----------------------------------------
|
|
No asynchronous control signals found in this design
|
|
|
|
Timing Summary:
|
|
---------------
|
|
Speed Grade: -5
|
|
|
|
Minimum period: 12.278ns (Maximum Frequency: 81.445MHz)
|
|
Minimum input arrival time before clock: No path found
|
|
Maximum output required time after clock: 4.326ns
|
|
Maximum combinational path delay: No path found
|
|
|
|
Timing Detail:
|
|
--------------
|
|
All values displayed in nanoseconds (ns)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'VGADriver/FRAME1'
|
|
Clock period: 12.278ns (frequency: 81.445MHz)
|
|
Total number of paths / destination ports: 614702 / 124
|
|
-------------------------------------------------------------------------
|
|
Delay: 12.278ns (Levels of Logic = 16)
|
|
Source: lp_6 (FF)
|
|
Destination: son (FF)
|
|
Source Clock: VGADriver/FRAME1 rising
|
|
Destination Clock: VGADriver/FRAME1 rising
|
|
|
|
Data Path: lp_6 to son
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDE:C->Q 19 0.514 0.925 lp_6 (lp_6)
|
|
LUT4:I3->O 5 0.612 0.607 hper_add0001<10>11 (hper_add0001<10>_bdd0)
|
|
LUT2:I1->O 1 0.612 0.000 hper_add0001<9>11 (hper_add0001<9>1)
|
|
MUXCY:S->O 0 0.404 0.000 Madd_prescaler_add0002_cy<9> (Madd_prescaler_add0002_cy<9>)
|
|
XORCY:CI->O 1 0.699 0.426 Madd_prescaler_add0002_xor<10> (prescaler_add0002<10>)
|
|
LUT2:I1->O 1 0.612 0.000 Mcompar_prescaler_cmp_le0003_lut<10> (Mcompar_prescaler_cmp_le0003_lut<10>)
|
|
MUXCY:S->O 3 0.752 0.454 Mcompar_prescaler_cmp_le0003_cy<10> (prescaler_cmp_le0003)
|
|
LUT4_D:I3->O 21 0.612 0.962 son_not0001557_1 (son_not0001557)
|
|
LUT4:I3->O 1 0.612 0.000 prescaler_mux0000<0>2 (prescaler_mux0000<0>)
|
|
MUXCY:S->O 1 0.404 0.000 Mcompar_son_cmp_lt0006_cy<0> (Mcompar_son_cmp_lt0006_cy<0>)
|
|
MUXCY:CI->O 1 0.052 0.000 Mcompar_son_cmp_lt0006_cy<1> (Mcompar_son_cmp_lt0006_cy<1>)
|
|
MUXCY:CI->O 1 0.052 0.000 Mcompar_son_cmp_lt0006_cy<2> (Mcompar_son_cmp_lt0006_cy<2>)
|
|
MUXCY:CI->O 1 0.052 0.000 Mcompar_son_cmp_lt0006_cy<3> (Mcompar_son_cmp_lt0006_cy<3>)
|
|
MUXCY:CI->O 1 0.052 0.000 Mcompar_son_cmp_lt0006_cy<4> (Mcompar_son_cmp_lt0006_cy<4>)
|
|
MUXCY:CI->O 1 0.052 0.000 Mcompar_son_cmp_lt0006_cy<5> (Mcompar_son_cmp_lt0006_cy<5>)
|
|
MUXCY:CI->O 21 0.399 0.962 Mcompar_son_cmp_lt0006_cy<6> (Mcompar_son_cmp_lt0006_cy<6>)
|
|
LUT4:I3->O 1 0.612 0.357 son_not000137 (son_not0001)
|
|
FDE:CE 0.483 son
|
|
----------------------------------------
|
|
Total 12.278ns (7.585ns logic, 4.693ns route)
|
|
(61.8% logic, 38.2% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'CLK'
|
|
Clock period: 7.122ns (frequency: 140.416MHz)
|
|
Total number of paths / destination ports: 10442 / 122
|
|
-------------------------------------------------------------------------
|
|
Delay: 7.122ns (Levels of Logic = 38)
|
|
Source: SpeakerDriver/prescaler_1 (FF)
|
|
Destination: SpeakerDriver/prescaler_24 (FF)
|
|
Source Clock: CLK rising
|
|
Destination Clock: CLK rising
|
|
|
|
Data Path: SpeakerDriver/prescaler_1 to SpeakerDriver/prescaler_24
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDR:C->Q 2 0.514 0.532 SpeakerDriver/prescaler_1 (SpeakerDriver/prescaler_1)
|
|
LUT1:I0->O 1 0.612 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<0>_rt (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<0>_rt)
|
|
MUXCY:S->O 1 0.404 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<0> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<0>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<1> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<1>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<2> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<2>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<3> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<3>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<4> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<4>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<5> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<5>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<6> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<6>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<7> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<7>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<8> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<8>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<9> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<9>)
|
|
MUXCY:CI->O 26 0.288 1.140 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<10> (SpeakerDriver/sout_cmp_ge0000)
|
|
LUT2:I1->O 1 0.612 0.000 SpeakerDriver/Madd_prescaler_add0000_lut<0> (SpeakerDriver/Madd_prescaler_add0000_lut<0>)
|
|
MUXCY:S->O 1 0.404 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<0> (SpeakerDriver/Madd_prescaler_add0000_cy<0>)
|
|
MUXCY:CI->O 1 0.052 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<1> (SpeakerDriver/Madd_prescaler_add0000_cy<1>)
|
|
MUXCY:CI->O 1 0.052 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<2> (SpeakerDriver/Madd_prescaler_add0000_cy<2>)
|
|
MUXCY:CI->O 1 0.052 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<3> (SpeakerDriver/Madd_prescaler_add0000_cy<3>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<4> (SpeakerDriver/Madd_prescaler_add0000_cy<4>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<5> (SpeakerDriver/Madd_prescaler_add0000_cy<5>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<6> (SpeakerDriver/Madd_prescaler_add0000_cy<6>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<7> (SpeakerDriver/Madd_prescaler_add0000_cy<7>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<8> (SpeakerDriver/Madd_prescaler_add0000_cy<8>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<9> (SpeakerDriver/Madd_prescaler_add0000_cy<9>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<10> (SpeakerDriver/Madd_prescaler_add0000_cy<10>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<11> (SpeakerDriver/Madd_prescaler_add0000_cy<11>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<12> (SpeakerDriver/Madd_prescaler_add0000_cy<12>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<13> (SpeakerDriver/Madd_prescaler_add0000_cy<13>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<14> (SpeakerDriver/Madd_prescaler_add0000_cy<14>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<15> (SpeakerDriver/Madd_prescaler_add0000_cy<15>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<16> (SpeakerDriver/Madd_prescaler_add0000_cy<16>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<17> (SpeakerDriver/Madd_prescaler_add0000_cy<17>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<18> (SpeakerDriver/Madd_prescaler_add0000_cy<18>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<19> (SpeakerDriver/Madd_prescaler_add0000_cy<19>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<20> (SpeakerDriver/Madd_prescaler_add0000_cy<20>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<21> (SpeakerDriver/Madd_prescaler_add0000_cy<21>)
|
|
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<22> (SpeakerDriver/Madd_prescaler_add0000_cy<22>)
|
|
MUXCY:CI->O 0 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<23> (SpeakerDriver/Madd_prescaler_add0000_cy<23>)
|
|
XORCY:CI->O 1 0.699 0.000 SpeakerDriver/Madd_prescaler_add0000_xor<24> (SpeakerDriver/prescaler_add0000<24>)
|
|
FDR:D 0.268 SpeakerDriver/prescaler_24
|
|
----------------------------------------
|
|
Total 7.122ns (5.449ns logic, 1.672ns route)
|
|
(76.5% logic, 23.5% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
|
|
Total number of paths / destination ports: 11 / 11
|
|
-------------------------------------------------------------------------
|
|
Offset: 4.326ns (Levels of Logic = 1)
|
|
Source: VGADriver/RGB_7 (FF)
|
|
Destination: RGB<7> (PAD)
|
|
Source Clock: CLK rising
|
|
|
|
Data Path: VGADriver/RGB_7 to RGB<7>
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDR:C->Q 8 0.514 0.643 VGADriver/RGB_7 (VGADriver/RGB_7)
|
|
OBUF:I->O 3.169 RGB_0_OBUF (RGB<0>)
|
|
----------------------------------------
|
|
Total 4.326ns (3.683ns logic, 0.643ns route)
|
|
(85.1% logic, 14.9% route)
|
|
|
|
=========================================================================
|
|
|
|
|
|
Total REAL time to Xst completion: 10.00 secs
|
|
Total CPU time to Xst completion: 9.75 secs
|
|
|
|
-->
|
|
|
|
Total memory usage is 225232 kilobytes
|
|
|
|
Number of errors : 0 ( 0 filtered)
|
|
Number of warnings : 61 ( 0 filtered)
|
|
Number of infos : 4 ( 0 filtered)
|
|
|